High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
In recent years, there has been an effort to reduce an area of a peripheral circuit region that is occupied by peripheral circuitry included on a semiconductor die of a memory device. For example, U.S. Pat. No. 6,151,257 describes an electronic circuit die including a plurality of first and second input/output pad buffer cells, where one of the first input/output buffer cells includes at least a latch for latching data signals and one of the second input/output pad buffer cells includes a pad that receives clock signal which are supplied to the latches of the first I/O pad buffer cells. As a result of this design, the conductive traces between the latches and the core logic need not be precisely matched, thus reducing cost. Another example is U.S. Pat. No. 7,023,742, which describes a semiconductor device and a method for inputting and outputting data simultaneously through a single pad. The semiconductor device includes an output buffer and an input buffer, and further includes first and second switching circuits. Another example is U.S. patent application publication 2007/0253267 A1, that describes a semiconductor device including a shared sense amplifier portion that has a driver transistor implemented by a ring-shaped gate electrode. Thus, the shared sense amplifier portion can be effective in the chip size reduction while an unbalance due to Kink effect can be reduced.